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25LC080C 25LC320A 25LC080D 25LC640A 25LC160C 25LC128 25LC160D 25LC256 8K-256K SPI Serial EEPROM High Temp Family Data Sheet
Features:
* Max. Clock 5 MHz * Low-power CMOS Technology: - Max. Write Current: 5 mA at 5.5V, 5 MHz - Read Current: 5 mA at 5.5V, 5 MHz - Standby Current: 10 A at 5.5V * 1024 x 8 through 32768 x 8-bit Organization * Byte and Page-level Write Operations * Self-timed Erase and Write Cycles (6 ms max.) * Block Write Protection: - Protect none, 1/4, 1/2 or all of array * Built-in Write Protection: - Power-on/off data protection circuitry - Write enable latch - Write-protect pin * Sequential Read * High Reliability: - Endurance: >1M erase/write cycles - Data retention: > 200 years - ESD protection: > 4000V * Temperature Range Supported: - Extended (H): -40C to +150C * Package is Pb-free and RoHS Compliant
Description:
Microchip Technology Inc. 25LCXXX* devices are Middensity 8 through 256 Kbit Serial Electrically Erasable PROMs (EEPROM). The devices are organized in blocks of x8-bit memory and support the Serial Peripheral Interface (SPI) compatible serial bus architecture. Byte-level and page-level functions are supported. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 25LCXXX is available in a standard 8-lead SOIC package. The package is Pb-free.
Package Types (not to scale)
SOIC (SN)
CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI
Pin Function Table
Name CS SO WP VSS SI SCK HOLD VCC Function Chip Select Input Serial Data Output Write-Protect Ground Serial Data Input Serial Clock Input Hold Input Supply Voltage
*25LCXXX is used in this document as a generic part number for the 25 series devices.
(c) 2009 Microchip Technology Inc.
Preliminary
DS22131C-page 1
25LCXXX
Device Selection Table
Part Number 25LC080C 25LC080D 25LC160C 25LC160D 25LC320A 25LC640A 25LC128 25LC256 Density (bits) 8K 8K 16K 16K 32K 64K 128K 256K Organization 1,024 x 8 1,024 x 8 2,048 x 8 2,048 x 8 4,096 x 8 8,192 x 8 16,384 x 8 32,768 x 8 VCC Range 2.5V - 5.5V 2.5V - 5.5V 2.5V - 5.5V 2.5V - 5.5V 2.5V - 5.5V 2.5V - 5.5V 2.5V - 5.5V 2.5V - 5.5V Max Speed (MHz) 5 5 5 5 5 5 5 5 Page Size (Bytes) 16 32 16 32 32 32 64 64 Temp. Range H H H H H H H H Package SN SN SN SN SN SN SN SN
DS22131C-page 2
Preliminary
(c) 2009 Microchip Technology Inc.
25LCXXX
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings()
VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V Storage temperature ................................................................................................................................. -65C to 155C Ambient temperature under bias........................................................................................................... -40C to 150C(1) ESD protection on all pins.......................................................................................................................................... 4 kV
Note 1: AEC-Q100 reliability testing for devices intended to operate at 150C is 1,000 hours. Any design in which the total operating time between 125C and 150C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc.
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Extended (H): Min. .7 VCC -0.3 -0.3 -- -- VCC -0.5 -- -- -- TA = -40C to +150C Max. VCC+1 0.3VCC 0.2VCC 0.4 0.2 -- 2 2 7 Units V V V V V V A A pF VCC 2.7V VCC < 2.7V IOL = 2.1 mA IOL = 1.0 mA IOH = -400 A CS = VCC, VIN = VSS OR VCC CS = VCC, VOUT = VSS OR VCC TA = 25C, CLK = 1.0 MHz, VCC = 5.0V (Note) VCC = 5.5V; FCLK = 5.0 MHz; SO = Open VCC = 2.5V; FCLK = 3.0 MHz; SO = Open VCC = 5.5V VCC = 2.5V CS = VCC = 5.5V, Inputs tied to VCC or VSS, 150C VCC = 2.5V to 5.5V Test Conditions
DC CHARACTERISTICS Param. No. D001 D002 D003 D004 D005 D006 D007 D008 D009 Sym. VIH1 VIL1 VIL2 VOL1 VOL2 VOH ILI ILO CINT Characteristic High-level input voltage Low-level input voltage Low-level output voltage High-level output voltage Input leakage current Output leakage current Internal Capacitance (all inputs and outputs)
D010
ICC Read Operating Current
-- --
5 2.5
mA mA mA mA A
D011 D012 Note:
ICC Write ICCS Standby Current
-- -- --
5 3 10
This parameter is periodically sampled and not 100% tested.
(c) 2009 Microchip Technology Inc.
Preliminary
DS22131C-page 3
25LCXXX
TABLE 1-2: AC CHARACTERISTICS
Extended (H): Min. -- -- 100 150 200 250 50 20 30 40 50 -- -- 100 150 100 150 50 50 -- -- 0 -- -- 40 80 40 80 60 160 60 160 -- 1,000,000 TA = -40C to +150C Max. 5 3 -- -- -- -- -- -- -- -- -- 2 2 -- -- -- -- -- -- 100 160 -- 80 160 -- -- -- -- -- -- -- -- 6 -- Units MHz MHz ns ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms VCC = 2.5V to 5.5V Test Conditions 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V -- 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V (Note 1) (Note 1) 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V -- -- 4.5V Vcc 5.5V 2.5V Vcc < 4.5V (Note 1) 4.5V Vcc 5.5V(Note 1) 2.5V Vcc 4.5V(Note 1) 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 4.5V Vcc 5.5V(Note 1) 2.5V Vcc < 4.5V(Note 1) 4.5V Vcc 5.5V 2.5V Vcc < 4.5V (Note 2) AC CHARACTERISTICS Param. Sym. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 FCLK TCSS TCSH TCSD Tsu THD TR TF THI TLO TCLD TCLE TV THO TDIS THS THH THZ THV TWC -- Characteristic Clock Frequency CS Setup Time CS Hold Time CS Disable Time Data Setup Time Data Hold Time CLK Rise Time CLK Fall Time Clock High Time Clock Low Time Clock Delay Time Clock Enable Time Output Valid from Clock Low Output Hold Time Output Disable Time HOLD Setup Time HOLD Hold Time HOLD Low to Output High-Z HOLD High to Output Valid Internal Write Cycle Time Endurance
E/W Page Mode, 25C, VCC = 5.5V (Note 3) Cycles
Note 1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained from our web site: www.microchip.com.
DS22131C-page 4
Preliminary
(c) 2009 Microchip Technology Inc.
25LCXXX
TABLE 1-3:
AC Waveform: VLO = 0.2V VHI = VCC - 0.2V VHI = 4.0V CL = 50 pF Timing Measurement Reference Level Input Output Note 1: For VCC 4.0V 2: For VCC > 4.0V 0.5 VCC 0.5 VCC -- (Note 1) (Note 2) --
AC TEST CONDITIONS
(c) 2009 Microchip Technology Inc.
Preliminary
DS22131C-page 5
25LCXXX
FIGURE 1-1:
CS 16 SCK 18 SO n+2 n+1 n High-Impedance 19 n 5 n n-1 n-1 17 16 17
HOLD TIMING
Don't Care SI HOLD n+2 n+1 n
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS 2 Mode 1,1 SCK Mode 0,0 5 SI 6 LSB in 7 8 3
12 11
MSB in
SO
High-Impedance
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS 9 SCK 13 14 SO MSB out 15 ISB out 10 3 Mode 1,1 Mode 0,0
SI
Don't Care
DS22131C-page 6
Preliminary
(c) 2009 Microchip Technology Inc.
25LCXXX
2.0 PIN DESCRIPTIONS
The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25LCXXX in a system with WP pin grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is set high. The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name CS SO WP VSS SI SCK HOLD VCC
PIN FUNCTION TABLE
Pin Number 1 2 3 4 5 6 7 8 Function Chip Select Input Serial Data Output Write-Protect Pin Ground Serial Data Input Serial Clock Input Hold Input Supply Voltage
2.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock.
2.5
Serial Clock (SCK)
2.1
Chip Select (CS)
A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence being initiated.
The SCK is used to synchronize the communication between a master and the 25LCXXX. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input.
2.6
Hold (HOLD)
2.2
Serial Output (SO)
The SO pin is used to transfer data out of the 25LCXXX. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock.
2.3
Write-Protect (WP)
The HOLD pin is used to suspend transmission to the 25LCXXX while in the middle of a serial sequence without having to retransmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-tolow transition. The 25LCXXX must remain selected during this sequence. The SI, SCK and SO pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line.
This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write.
(c) 2009 Microchip Technology Inc.
Preliminary
DS22131C-page 7
25LCXXX
3.0
3.1
FUNCTIONAL DESCRIPTION
Principles of Operation
Block Diagram
STATUS Register HV Generator
The 25LCXXX are Mid-Density Serial EEPROMs designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today's popular microcontroller families, including Microchip's PIC(R) microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/ O lines programmed properly in firmware to match the SPI protocol. The 25LCXXX contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25LCXXX in `HOLD' mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted.
I/O Control Logic
Memory Control Logic
X Dec
EEPROM Array
Page Latches
SI SO CS SCK HOLD WP VCC VSS
Y Decoder
Sense Amp. R/W Control
TABLE 3-1:
INSTRUCTION SET
Instruction Format Description Read data from memory array beginning at selected address Write data to memory array beginning at selected address Reset the write enable latch (disable write operations) Set the write enable latch (enable write operations) Read STATUS register Write STATUS register
Instruction Name READ WRITE WRDI WREN RDSR WRSR
0000 0011 0000 0010 0000 0100 0000 0110 0000 0101 0000 0001
DS22131C-page 8
Preliminary
(c) 2009 Microchip Technology Inc.
25LCXXX
3.2 Read Sequence
The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25LCXXX followed by the 16-bit address. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1). Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, and then the data to be written. Depending upon the density, a page of data that ranges from 16 bytes to 64 bytes can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or `page size') and, end at addresses that are integer multiples of page size - 1. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
3.3
Write Sequence
Prior to any attempt to write data to the 25LCXXX, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25LCXXX. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set.
For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset.
FIGURE 3-1:
CS 0 SCK
READ SEQUENCE
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
Instruction SI 0 0 0 0 0 0 1
16-bit Address 1 15 14 13 12 2 1 0 Data Out 7 6 5 4 3 2 1 0
High-Impedance SO
(c) 2009 Microchip Technology Inc.
Preliminary
DS22131C-page 9
25LCXXX
FIGURE 3-2:
CS Twc 0 SCK Instruction SI 0 0 0 0 0 0 1 16-bit Address 0 15 14 13 12 2 1 0 7 6 Data Byte 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31
BYTE WRITE SEQUENCE
High-Impedance SO
FIGURE 3-3:
CS 0 SCK 1
PAGE WRITE SEQUENCE
2
3
4
5
6
7
8
9 10 11 16-bit Address
21 22 23 24 25 26 27 28 29 30 31 Data Byte 1 2 1 0 7 6 5 4 3 2 1 0
Instruction SI 0 0 0 0 0 01
0 15 14 13 12
CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2 1 0 7 6 Data Byte 3 5 4 3 2 1 0 7
Data Byte n (16/32/64 max)
6
5
4
3
2
1
0
DS22131C-page 10
Preliminary
(c) 2009 Microchip Technology Inc.
25LCXXX
3.4 Write Enable (WREN) and Write Disable (WRDI)
The following is a list of conditions under which the write enable latch will be reset: * * * * Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed
The 25LCXXX contains a write enable latch. See Table 5-1 for the write-protect functionality matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch.
FIGURE 3-4:
WRITE ENABLE SEQUENCE (WREN)
CS 0 SCK 1 2 3 4 5 6 7
SI
0
0
0
0
0
1
1
0
High-Impedance SO
FIGURE 3-5:
WRITE DISABLE SEQUENCE (WRDI)
CS 0 SCK 1 2 3 4 5 6 7
SI
0
0
0
0
0
1
0 1
0
High-Impedance SO
(c) 2009 Microchip Technology Inc.
Preliminary
DS22131C-page 11
25LCXXX
3.5 Read Status Register Instruction (RDSR)
The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. When set to a `1', the latch allows writes to the array, when set to a `0', the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the STATUS register. These commands are shown in Figure 3-4 and Figure 3-5. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile, and are shown in Table 3-3. See Figure 3-6 for the RDSR timing sequence.
The Read Status Register instruction (RDSR) provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows:
TABLE 3-2:
STATUS REGISTER
0 R WIP
7 654 3 2 1 W/R - - - W/R W/R R WPEN X X X BP1 BP0 WEL W/R = writable/readable. R = read-only.
The Write-In-Process (WIP) bit indicates whether the 25LCXXX is busy with a write operation. When set to a `1', a write is in progress, when set to a `0', no write is in progress. This bit is read-only.
FIGURE 3-6:
CS
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
0 SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Instruction SI 0 0 0 0 0 1 0 1
High-Impedance SO 7
Data from STATUS Register 6 5 4 3 2 1 0
DS22131C-page 12
Preliminary
(c) 2009 Microchip Technology Inc.
25LCXXX
3.6 Write Status Register Instruction (WRSR)
The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table 5-1 for a matrix of functionality on the WPEN bit. See Figure 3-7 for the WRSR timing sequence.
The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 3-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two or all four of the segments of the array. The partitioning is controlled as shown in Table 3-3.
TABLE 3-3:
BP1
ARRAY PROTECTION
BP0 Array Addresses Write-Protected None Upper 1/4 Upper 1/2 All Array Addresses Unprotected All Lower 3/4 Lower 1/2 None
0 0 1 1 TABLE 3-4:
Density
0 1 0 1
ARRAY PROTECTED ADDRESS LOCATIONS
Upper 1/4 Upper 1/2 200h - 3FFh 400h - 7FFh 800h - FFFh 1000h - 1FFFh 2000h - 3FFFh 4000h - 7FFFh All 000h - 3FFh 000h - 7FFh 000h - FFFh 0000h - 1FFFh 0000h - 3FFFh 0000h - 7FFFh
8K 16K 32K 64K 128K 256K FIGURE 3-7:
CS 0 SCK 1 2
300h - 3FFh 600h - 7FFh C00h - FFFh 1800h - 1FFFh 3000h - 3FFFh 6000h - 7FFFh
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
3
4
5
6
7
8
9
10
11
12
13
14
15
Instruction SI 0 0 0 0 0 0 0 1 7 6
Data to STATUS Register 5 4 3 2 1 0
High-Impedance SO Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register sequence.
(c) 2009 Microchip Technology Inc.
Preliminary
DS22131C-page 13
25LCXXX
4.0 DATA PROTECTION 5.0 POWER-ON STATE
The following protection has been implemented to prevent inadvertent writes to the array: * The write enable latch is reset on power-up * A write enable instruction must be issued to set the write enable latch * After a byte write, page write or STATUS register write, the write enable latch is reset * CS must be set high after the proper number of clock cycles to start an internal write cycle * Access to the array during an internal write cycle is ignored and programming is continued The 25LCXXX powers on in the following state: * The device is in low-power Standby mode (CS = 1) * The write enable latch is reset * SO is in high-impedance state * A high-to-low-level transition on CS is required to enter active state
TABLE 5-1:
WEL (SR bit 1) 0 1 1 1 x = don't care
WRITE-PROTECT FUNCTIONALITY MATRIX
WPEN (SR bit 7) x 0 1 1 WP (pin 3) x x 0 (low) 1 (high) Protected Blocks Protected Protected Protected Protected Unprotected Blocks Protected Writable Writable Writable STATUS Register Protected Writable Protected Writable
DS22131C-page 14
Preliminary
(c) 2009 Microchip Technology Inc.
25LCXXX
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
8-Lead SOIC
Example:
XXXXXXXT XXXXYYWW NNN
25LC32AH SN e3 0728 1L7
8-Lead SOIC Package Marking (Pb-Free) Device 25LC080C 25LC080D 25LC160C 25LC160D 25LC320A 25LC640A 25LC128 25LC256 Note 1: T = Temperature Grade (H). Line 1 Marking 25LC80CT 25LC80DT 25LC16CT 25LC16DT 25LC32AT 25L640AT 25LC128T 25LC256T
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Custom marking available.
Note:
(c) 2009 Microchip Technology Inc.
Preliminary
DS22131C-page 15
25LCXXX
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DS22131C-page 16
Preliminary
(c) 2009 Microchip Technology Inc.
25LCXXX
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(c) 2009 Microchip Technology Inc.
Preliminary
DS22131C-page 17
25LCXXX
REVISION HISTORY
Revision A (01/2009)
Original Release.
Revision B (04/2009)
Revised part number from 25XX to 25LCXXX; Added Note 1 to Electrical Characteristics.
Revision C (06/2009)
Revised Features: Endurance and Package; Revised Table 1-2, Para. 21.
DS22131C-page 18
Preliminary
(c) 2009 Microchip Technology Inc.
25LCXXX
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
(c) 2009 Microchip Technology Inc.
Preliminary
DS22131C-page 19
25LCXXX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: 25LCXXX Questions: 1. What are the best features of this document? Y N Literature Number: DS22131C FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS22131C-page 20
Preliminary
(c) 2009 Microchip Technology Inc.
25LCXXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Tape & Reel
-
X Temp Range
/XX Package
Examples:
a) 25LC080CT-H/SN = 8k-bit, 16-byte page, 2.5V Serial EEPROM, Extended temp., Tape & Reel, SOIC package 25LC080D-H/SN = 8k-bit, 32-byte page, 2.5V Serial EEPROM, Extended temp., SOIC package 25LC160CT-H/SN = 16k-bit, 16-byte page, 2.5V Serial EEPROM, Extended temp., Tape & Reel, SOIC package 25LC160D-H/SN = 16k-bit, 32-byte page, 2.5V Serial EEPROM, Extended temp., SOIC package 25LC320AT-H/SN = 32k-bit, 32-byte page, 2.5V Serial EEPROM, Extended temp., Tape & Reel, SOIC package 25LC640A-H/SN = 64k-bit, 32-byte page, 2.5V Serial EEPROM, Extended temp., SOIC package 25LC128T-H/SN = 128k-bit, 64-byte page, 2.5V Serial EEPROM, Extended temp., Tape & Reel, SOIC package 25LC256-H/SN = 256k-bit, 64-byte page, 2.5V Serial EEPROM, Extended temp., SOIC package
Device:
25LC080C = 25LC080D = 25LC160C = 25LC160D = 25LC320A = 25LC640A = 25LC128 = 25LC256 = Blank T H = = =
8k-bit, 2.5V, 16 Byte Page, SPI Serial EEPROM 8k-bit, 2.5V, 32 Byte Page, SPI Serial EEPROM 16k-bit, 2.5V, 16 Byte Page, SPI Serial EEPROM 16k-bit, 2.5V, 32 Byte Page, SPI Serial EEPROM 32k-bit, 2.5V, 32 Byte Page, SPI Serial EEPROM 64k-bit, 2.5V, 32 Byte Page, SPI Serial EEPROM 128k-bit, 2.5V, 64 Byte Page, SPI Serial EEPROM 256k-bit, 2.5V, 64 Byte Page, SPI Serial EEPROM Standard packaging Tape & Reel -40C to+150C
b)
c)
d)
Tape & Reel: Temperature Range:
e)
f) SN = Plastic SOIC (3.90 mm body), 8-lead
Package:
g)
h)
(c) 2009 Microchip Technology Inc.
Preliminary
DS22131C-page 21
25LCXXX
NOTES:
DS22131C-page 22
Preliminary
(c) 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, Omniscient Code Generation, PICC, PICC-18, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2009 Microchip Technology Inc.
Preliminary
DS22131C-page 23
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
03/26/09
DS22131C-page 24
Preliminary
(c) 2009 Microchip Technology Inc.

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